1. Field of the Invention
The present invention generally relates to PLL (phase-locked loop) devices, and particularly relates to a PLL device which generates a clock signal synchronized with an input clock signal.
In recent years, there has been an increasing demand for a cost reduction in designing communication devices which are faster in signal transmission. In order to meet this demand, a PLL device that is highly accurate and reliable in high-speed signal transmission is required without incurring a high design cost.
2. Description of the Related Art
FIG. 1 is a block diagram showing a configuration of a related-art PLL device. This PLL device is implemented as an analog circuit.
In FIG. 1, a phase comparator 10 compares an input signal with an output clock signal in terms of their phases. A resulting phase-difference signal is supplied to a filter 12, where high-frequency components of the signal are removed, and is then supplied to a voltage generator 14. Based on the supplied signal, the voltage generator 14 generates a voltage level, which is provided to a VCO 16. The VCO 16 generates a pulse signal having a frequency commensurate with the supplied voltage, and this pulse signal is output as the output clock signal.
FIG. 2 is a block diagram showing another configuration of a related-art PLL device. This PLL device is implemented as a digital circuit.
In FIG. 2, communication data in an input signal includes synchronization bits. When a synchronization-bit detector 20 detects the synchronization bits in the input signal, the synchronization-bit detector 20 supplies a detection signal to the indicator 22. The indicator 22 also receives a clock signal which has a frequency N times as high as that of the input signal. The indicator 22 determines which clock pulse of the received clock signal identified in relation to the timing of the detection signal should be used as a synchronization clock pulse in order to maintain synchronization with the input signal until next synchronization bits are supplied. The indicator 22 then gives an instruction to a selector 24. The selector 24 selectively extracts identified pulse of the received clock signal once in every N pulses, and outputs the extracted pulses as a synchronization clock signal.
FIG. 3 is a block diagram showing a configuration of a related-art PLL device. This PLL device is implemented as a digital circuit.
In FIG. 3, an input signal is successively delayed by delay units 30.sub.1 through 30.sub.N . Respective outputs of the delay units 30.sub.1 through 30.sub.N are supplied to a selector 32. Further, a phase comparator 34 compares the input signal with an output clock signal in terms of their phases. A resulting phase-difference signal is supplied to the selector 32. Based on the phase-difference signal, the selector 32 selects one of the outputs of the delay units 30.sub.1 through 30.sub.N so as to eliminate the phase difference. The selected signal is supplied as the output clock signal from a pulse generator 36.
The PLL circuit of FIG. 1 is capable of generating a highly accurate clock signal, but requires a sophisticated control of the phase comparator 10, the voltage generator 14, and the VCO 16. Further, complexity of each circuit results in an undesirably large circuit volume. Analog control is susceptible to a change in temperature, so that a malfunction may occur when noise is introduced into the output signal of the voltage generator 14. A high level of skill is required to design a circuit which can eliminate such noise, thereby adding to the overall cost of the device.
The PLL device of FIG. 2 can maintain a circuit size thereof lower than that of the PLL circuit of FIG. 1, thereby providing a low cost PLL device. However, accuracy achieved by this device is not so high, and a phase displacement is generated in a relatively short period of time. In order to avoid this, the input signal needs to be provided with the synchronization bits at rather short intervals. In this case, a need to establish synchronism rather frequently leads to a degradation in a signal-transmission rate.
The PLL device of FIG. 3 needs a large number of delay units in order to achieve a higher accuracy than the PLL device of FIG. 2, thereby resulting in a large circuit volume. Further, the delay units are susceptible to a variation in delay lengths due to a variation in a process of making a semiconductor device. This gives rise to a problem that a macro structure is difficult to achieve.
Accordingly, there is a need for a PLL device which can reduce a design time, cost, and circuit size while being capable of coping with a wide range of a frequency variation of an input signal with a sufficient accuracy, and can avoid a degradation in a signal-transmission rate by avoiding insertion of synchronization bits into the input signal.